Cortex-A 系列处理器Cortex-A77文档分享 |arm_cortex_a77_mp074_software_developer_errata_notice_v9.0

1 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Arm Cortex-A77 MP074 Software Developer Errata Notice This document contains all known errata since the r0p0 release of the product. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 1 of 59 Non-confidential 

2 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Non-Confidential Proprietary notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, patents, copyrights, trade secrets, or other rights. This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document at any time and without notice. If any of the provisions contained in these terms conflict with any of the provisions of any click through or signed written agreement covering this document with Arm, then the click through or signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail. The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at http://www.arm.com/ company/policies/trademarks. Copyright © 2019 Arm Limited (or its affiliates). All rights reserved. Arm Limited. Company 02557590 registered in England. 110 Fulbourn Road, Cambridge, England CB1 9NJ. LES-PRE-20349 Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. Web address http://www.arm.com/. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 2 of 59 Non-confidential 

3 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version. • An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. Feedback on this document If you have comments on content then send an e-mail to errata@arm.com giving: • The document title. • The document number: SDEN-1152370. • If applicable, the page number(s) to which your comments refer. • A concise explanation of your comments. Arm also welcomes general suggestions for additions and improvements. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 3 of 59 Non-confidential 

4 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Contents INTRODUCTION 7 ERRATA SUMMARY TABLE 13 1316063 Modification of the translation table for a virtual page which is being accessed by an active 16 process might lead to read-after-write ordering violation 1160841 Continuous failing STREX because of another core snooping from speculatively executed 17 atomic behind constantly mispredicted branch might cause livelock 1177367 Speculative AT instruction using out-of-context translation regime could cause subsequent 18 request to generate an incorrect translation Status 1191167 MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect 19 result 1204882 The exclusive monitor might end up tracking an incorrect cache line in the presence of a VA- 20 alias, causing a false pass on the exclusive access sequence 1220737 Streaming store under specific conditions might cause deadlock or data corruption 21 1253791 Multiple floating-point divides/square roots concurrently completing back-to-back and 22 flushing back-to-back might cause data corruption Status 1262841 Translation access hitting a prefetched L2 TLB entry under specific conditions might corrupt 23 the L2 TLB leading to an incorrect translation 1273521 A T32 instruction inside an IT block followed by mispredicted speculative instruction stream 24 might cause a deadlock 1450698 Software Step might prevent interrupt recognition 25 1467687 Branch prediction for an ERET cached in the instruction cache might cause a deadlock 27 1508412 NC/Device Load and Store Exclusive or PAR-Read collision can cause deadlock 28 1515815 The core might execute multiple instructions before taking a software step exception or halt 29 step exception when the executing instruction resides in the L0 Macro-op cache 1286809 Modification of the translation table for a virtual page which is being accessed by an active 29 process might lead to read-after-read ordering violation 1418842 MRRC reads of some Generic Timer system registers in AArch32 mode might return corrupt 31 data 1542418 The core might fetch a stale instruction from the L0 Macro-op cache which violates the 32 ordering of instruction fetches 1148171 ERR0MISC0 might report incorrect BANK and SUBBANK values for transient parity errors in 32 L1 instruction cache data array 1151664 Direct access to internal memory for L2 TLB might not update IDATAn_EL3 registers 34 1162083 16-bit T32 instruction close to breakpoint location may cause early breakpoint exception 35 1185469 Exception packet for return stack match might return incorrect [E1:E0] field 36 1192280 IMPLEMENTATION DEFINED fault for unsupported atomic operations is not routed to 37 proper Exception level 1207839 Software step might see extra instruction executed for some loads when crossed with snoop 38 invalidation or ECC error 1220404 Direct access to L1 data TLB might report incorrect value of valid bit of the corresponding 39 TLB entry 1220843 ERR0STATUS.SERR encoding is incorrect for error responses from slave and deferred data 40 errors from slave which are not supported 1244986 Illegal return event might corrupt PSTATE.UA0 41 1256789 Halting step might see extra instruction executed for some loads when crossed with snoop 42 invalidation or ECC error SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 4 of 59 Non-confidential 

5 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1262908 Write-Back load after two Device-nG* stores to the same physical address might get invalid 43 data 1328683 Uncontainable (UC) SError might be incorrectly logged as an Unrecoverable (UEU) SError 44 1346768 TLBI does not treat upper ASID bits as zero when TCR_EL1.AS is 0 45 1355135 L1D_CACHE access related PMU events and L1D_TLB access related PMU events 46 increment on instructions/micro-operations excluded from these events 1395535 Read from PMCCNTR in AArch32 might return corrupted data 47 1405548 MSR DSPSR_EL0 while in debug state might not correctly update PSTATE.{N,C,Z,V,GE} on 48 debug exit 1415321 LDREX-STREX might succeed incorrectly when an intervening store occurs and LDREX 49 detects a single-bit ECC error on the cache line in the L1 data cache tag RAM 1421023 Portions of the branch target address recorded in ETM trace information are incorrect for an 50 indirect branch with a malformed branch target address 1487187 Waypoints from previous session might cause single-shot comparator match when trace 51 enabled 1488613 An unaligned load might initiate a prefetch request which crosses a page boundary 52 1491015 TRCIDR3.CCITMIN value is incorrect 53 1514033 Error Synchronization Barrier (ESB) instruction execution with a pending masked Virtual 54 SError might not clear HCR_EL2.VSE 1519163 AMU Counter INST_RETIRED does not increment correctly when 16 instructions retire in 55 same cycle 1522097 The core might detect a breakpoint exception one instruction earlier than the programmed 56 location when the L0 Macro-op cache contains an instruction that is affected by a parity error 1523503 CPUECTLR_EL1 controls for the MMU have no affect 57 1610369 ERR0MISC0_EL1.SUBARRAY value for ECC errors in the L1 data cache might be incorrect 58 1624431 CPUAMEVTYPER4_EL0 register cannot be written 59 SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 5 of 59 Non-confidential 

6 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 r0p0 implementation fixes Note the following errata might be fixed in some implementations of r0p0. This can be determined by reading the REVIDR_EL1 register where a set bit indicates that the erratum is fixed in this part. REVIDR_EL1[0] 1220737 Streaming store under specific conditions might cause deadlock or data corruption Note that there is no change to the MIDR_EL1 which remains at r0p0 but the REVIDR_EL1 is updated to indicate which errata are corrected. Software will identify this release through the combination of MIDR_EL1 and REVIDR_EL1. r1p0 implementation fixes Note the following errata might be fixed in some implementations of r1p0. This can be determined by reading the REVIDR_EL1 register where a set bit indicates that the erratum is fixed in this part. REVIDR_EL1[0] 1316063 Modification of the translation table for a virtual page which is being accessed by an active process might lead to read after write ordering violation. Note that there is no change to the MIDR_EL1 which remains at r1p0 but the REVIDR_EL1 is updated to indicate which errata are corrected. Software will identify this release through the combination of MIDR_EL1 and REVIDR_EL1. r1p0 implementation fixes Note the following errata might be fixed in some implementations of r1p0. This can be determined by reading the REVIDR_EL1 register where a set bit indicates that the erratum is fixed in this part. REVIDR_EL1[3] 1450698 Software Step might prevent interrupt recognition Note that there is no change to the MIDR_EL1 which remains at r1p0 but the REVIDR_EL1 is updated to indicate which errata are corrected. Software will identify this release through the combination of MIDR_EL1 and REVIDR_EL1. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 6 of 59 Non-confidential 

7 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Introduction Scope This document describes errata categorized by level of severity. Each description includes: • The current status of the erratum. • Where the implementation deviates from the specification and the conditions required for erroneous behavior to occur. • The implications of the erratum with respect to typical applications. • The application and limitations of a workaround where possible. Categorization of errata Errata are split into three levels of severity and further qualified as common or rare: Category A A critical error. No workaround is available or workarounds are impactful. The error is likely to be common for many systems and applications. Category A (Rare) A critical error. No workaround is available or workarounds are impactful. The error is likely to be rare for most systems and applications. Rare is determined by analysis, verification and usage. Category B A significant error or a critical error with an acceptable workaround. The error is likely to be common for many systems and applications. Category B (Rare) A significant error or a critical error with an acceptable workaround. The error is likely to be rare for most systems and applications. Rare is determined by analysis, verification and usage. Category C A minor error. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 7 of 59 Non-confidential 

8 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Change control Errata are listed in this section if they are new to the document, or marked as “updated” if there has been any change to the erratum text. Fixed errata are not shown as updated unless the erratum text has changed. The errata summary table on page 13 identifies errata that have been fixed in each product revision. 08-Nov-2019: Changes in document version 9.0 ID Status Area Cat Summary of erratum 1467687 Updated Programmer CatB Branch prediction for an ERET cached in the instruction cache might cause a deadlock 1508412 Updated Programmer CatB NC/Device Load and Store Exclusive or PAR-Read collision can cause deadlock 1542418 New Programmer CatB The core might fetch a stale instruction from the (rare) L0 Macro-op cache which violates the ordering of instruction fetches 1514033 New Programmer CatC Error Synchronization Barrier (ESB) instruction execution with a pending masked Virtual SError might not clear HCR_EL2.VSE 1519163 New Programmer CatC AMU Counter INST_RETIRED does not increment correctly when 16 instructions retire in same cycle 1522097 New Programmer CatC The core might detect a breakpoint exception one instruction earlier than the programmed location when the L0 Macro-op cache contains an instruction that is affected by a parity error 1523503 New Programmer CatC CPUECTLR_EL1 controls for the MMU have no affect 1610369 New Programmer CatC ERR0MISC0_EL1.SUBARRAY value for ECC errors in the L1 data cache might be incorrect 1624431 New Programmer CatC CPUAMEVTYPER4_EL0 register cannot be written 15-Jul-2019: Changes in document version 8.0 ID Status Area Cat Summary of erratum 1508412 New Programmer CatB NC/Device Load and Store Exclusive or PAR-Read collision can cause deadlock 1515815 New Programmer CatB The core might execute multiple instructions before taking a software step exception or halt step exception when the executing instruction resides in the L0 Macro-op cache 1487187 New Programmer CatC Waypoints from previous session might cause single-shot comparator match when trace enabled 1488613 New Programmer CatC An unaligned load might initiate a prefetch request which crosses a page boundary 1491015 New Programmer CatC TRCIDR3.CCITMIN value is incorrect SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 8 of 59 Non-confidential 

9 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 24-May-2019: Changes in document version 7.0 ID Status Area Cat Summary of erratum 1450698 New Programmer CatB Software Step might prevent interrupt recognition 1467687 New Programmer CatB Branch prediction for an ERET cached in the instruction cache might cause a deadlock 29-Mar-2019: Changes in document version 6.0 ID Status Area Cat Summary of erratum 1418842 New Programmer CatB MRRC reads of some Generic Timer system (rare) registers in AArch32 mode might return corrupt data 1328683 New Programmer CatC Uncontainable (UC) SError might be incorrectly logged as an Unrecoverable (UEU) SError 1346768 New Programmer CatC TLBI does not treat upper ASID bits as zero when TCR_EL1.AS is 0 1355135 New Programmer CatC L1D_CACHE access related PMU events and L1D_TLB access related PMU events increment on instructions/micro-operations excluded from these events 1395535 New Programmer CatC Read from PMCCNTR in AArch32 might return corrupted data 1405548 New Programmer CatC MSR DSPSR_EL0 while in debug state might not correctly update PSTATE.{N,C,Z,V,GE} on debug exit 1415321 New Programmer CatC LDREX-STREX might succeed incorrectly when an intervening store occurs and LDREX detects a single-bit ECC error on the cache line in the L1 data cache tag RAM 1421023 New Programmer CatC Portions of the branch target address recorded in ETM trace information are incorrect for an indirect branch with a malformed branch target address 15-Mar-2019: Changes in document version 5.0 ID Status Area Cat Summary of erratum No new or updated errata in this document version. 03-Dec-2018: Changes in document version 4.0 ID Status Area Cat Summary of erratum 1316063 New Programmer CatA Modification of the translation table for a virtual (rare) page which is being accessed by an active process might lead to read-after-write ordering violation SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 9 of 59 Non-confidential 

10 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1286809 New Programmer CatB Modification of the translation table for a virtual (rare) page which is being accessed by an active process might lead to read-after-read ordering violation 05-Oct-2018: Changes in document version 3.0 ID Status Area Cat Summary of erratum 1160841 Updated Programmer CatB Continuous failing STREX because of another core snooping from speculatively executed atomic behind constantly mispredicted branch might cause livelock 1177367 Updated Programmer CatB Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation Status 1191167 Updated Programmer CatB MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result 1204882 Updated Programmer CatB The exclusive monitor might end up tracking an incorrect cache line in the presence of a VA-alias, causing a false pass on the exclusive access sequence 1220737 New Programmer CatB Streaming store under specific conditions might cause deadlock or data corruption 1253791 New Programmer CatB Multiple floating-point divides/square roots concurrently completing back-to-back and flushing back-to-back might cause data corruption Status 1262841 New Programmer CatB Translation access hitting a prefetched L2 TLB entry under specific conditions might corrupt the L2 TLB leading to an incorrect translation 1273521 New Programmer CatB A T32 instruction inside an IT block followed by mispredicted speculative instruction stream might cause a deadlock 1148171 Updated Programmer CatC ERR0MISC0 might report incorrect BANK and SUBBANK values for transient parity errors in L1 instruction cache data array 1151664 Updated Programmer CatC Direct access to internal memory for L2 TLB might not update IDATAn_EL3 registers 1162083 Updated Programmer CatC 16-bit T32 instruction close to breakpoint location may cause early breakpoint exception 1185469 Updated Programmer CatC Exception packet for return stack match might return incorrect [E1:E0] field 1192280 Updated Programmer CatC IMPLEMENTATION DEFINED fault for unsupported atomic operations is not routed to proper Exception level SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 10 of 59 Non-confidential 

11 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1207839 Updated Programmer CatC Software step might see extra instruction executed for some loads when crossed with snoop invalidation or ECC error 1220404 New Programmer CatC Direct access to L1 data TLB might report incorrect value of valid bit of the corresponding TLB entry 1220843 New Programmer CatC ERR0STATUS.SERR encoding is incorrect for error responses from slave and deferred data errors from slave which are not supported 1244986 New Programmer CatC Illegal return event might corrupt PSTATE.UA0 1256789 New Programmer CatC Halting step might see extra instruction executed for some loads when crossed with snoop invalidation or ECC error 1262908 New Programmer CatC Write-Back load after two Device-nG* stores to the same physical address might get invalid data 27-Jul-2018: Changes in document version 2.0 ID Status Area Cat Summary of erratum 1160841 New Programmer CatB Continuous failing STREX because of another core snooping from speculatively executed atomic behind constantly mispredicted branch might cause livelock 1177367 New Programmer CatB Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation Status 1191167 New Programmer CatB MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result 1204882 New Programmer CatB The exclusive monitor might end up tracking an incorrect cache line in the presence of a VA-alias, causing a false pass on the exclusive access sequence 1162083 New Programmer CatC 16-bit T32 instruction close to breakpoint location may cause early breakpoint exception 1185469 New Programmer CatC Exception packet for return stack match might return incorrect [E1:E0] field 1192280 New Programmer CatC IMPLEMENTATION DEFINED fault for unsupported atomic operations is not routed to proper Exception level 1207839 New Programmer CatC Software step might see extra instruction executed for some loads when crossed with snoop invalidation or ECC error 16-May-2018: Changes in document version 1.0 ID Status Area Cat Summary of erratum SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 11 of 59 Non-confidential 

12 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1148171 New Programmer CatC ERR0MISC0 might report incorrect BANK and SUBBANK values for transient parity errors in L1 instruction cache data array 1151664 New Programmer CatC Direct access to internal memory for L2 TLB might not update IDATAn_EL3 registers SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 12 of 59 Non-confidential 

13 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Errata summary table The errata associated with this product affect product versions as below. ID Cat Summary Found in versions Fixed in version 1316063 CatA (rare) Modification of the translation table r0p0, r1p0 r1p1 for a virtual page which is being accessed by an active process might lead to read-after-write ordering violation 1160841 CatB Continuous failing STREX because r0p0 r1p0 of another core snooping from speculatively executed atomic behind constantly mispredicted branch might cause livelock 1177367 CatB Speculative AT instruction using r0p0 r1p0 out-of-context translation regime could cause subsequent request to generate an incorrect translation Status 1191167 CatB MRC read following MRRC read of r0p0 r1p0 specific Generic Timer in AArch32 might give incorrect result 1204882 CatB The exclusive monitor might end r0p0 r1p0 up tracking an incorrect cache line in the presence of a VA- alias, causing a false pass on the exclusive access sequence 1220737 CatB Streaming store under specific r0p0 r1p0 conditions might cause deadlock or data corruption 1253791 CatB Multiple floating-point divides/ r0p0 r1p0 square roots concurrently completing back-to-back and flushing back-to-back might cause data corruption Status 1262841 CatB Translation access hitting a r0p0 r1p0 prefetched L2 TLB entry under specific conditions might corrupt the L2 TLB leading to an incorrect translation 1273521 CatB A T32 instruction inside an IT r0p0 r1p0 block followed by mispredicted speculative instruction stream might cause a deadlock 1450698 CatB Software Step might prevent r0p0, r1p0 r1p1 interrupt recognition 1467687 CatB Branch prediction for an ERET r0p0, r1p0 r1p1 cached in the instruction cache might cause a deadlock 1508412 CatB NC/Device Load and Store r0p0, r1p0 r1p1 Exclusive or PAR-Read collision can cause deadlock 1515815 CatB The core might execute multiple r0p0, r1p0 r1p1 instructions before taking a software step exception or halt step exception when the executing SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 13 of 59 Non-confidential 

14 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 ID Cat Summary Found in versions Fixed in version instruction resides in the L0 Macro- op cache 1286809 CatB (rare) Modification of the translation table r0p0, r1p0 r1p1 for a virtual page which is being accessed by an active process might lead to read-after-read ordering violation 1418842 CatB (rare) MRRC reads of some Generic r0p0, r1p0 r1p1 Timer system registers in AArch32 mode might return corrupt data 1542418 CatB (rare) The core might fetch a stale r0p0, r1p0 r1p1 instruction from the L0 Macro-op cache which violates the ordering of instruction fetches 1148171 CatC ERR0MISC0 might report incorrect r0p0 r1p0 BANK and SUBBANK values for transient parity errors in L1 instruction cache data array 1151664 CatC Direct access to internal memory r0p0 r1p0 for L2 TLB might not update IDATAn_EL3 registers 1162083 CatC 16-bit T32 instruction close to r0p0 r1p0 breakpoint location may cause early breakpoint exception 1185469 CatC Exception packet for return stack r0p0 r1p0 match might return incorrect [E1:E0] field 1192280 CatC IMPLEMENTATION DEFINED fault r0p0 r1p0 for unsupported atomic operations is not routed to proper Exception level 1207839 CatC Software step might see extra r0p0 r1p0 instruction executed for some loads when crossed with snoop invalidation or ECC error 1220404 CatC Direct access to L1 data TLB might r0p0 r1p0 report incorrect value of valid bit of the corresponding TLB entry 1220843 CatC ERR0STATUS.SERR encoding is r0p0 r1p0 incorrect for error responses from slave and deferred data errors from slave which are not supported 1244986 CatC Illegal return event might corrupt r0p0 r1p0 PSTATE.UA0 1256789 CatC Halting step might see extra r0p0 r1p0 instruction executed for some loads when crossed with snoop invalidation or ECC error 1262908 CatC Write-Back load after two Device- r0p0 r1p0 nG* stores to the same physical address might get invalid data 1328683 CatC Uncontainable (UC) SError might r0p0, r1p0 r1p1 be incorrectly logged as an Unrecoverable (UEU) SError 1346768 CatC TLBI does not treat upper ASID r0p0, r1p0, r1p1 Open bits as zero when TCR_EL1.AS is 0 SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 14 of 59 Non-confidential 

15 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 ID Cat Summary Found in versions Fixed in version 1355135 CatC L1D_CACHE access related PMU r0p0, r1p0 r1p1 events and L1D_TLB access related PMU events increment on instructions/micro-operations excluded from these events 1395535 CatC Read from PMCCNTR in AArch32 r0p0, r1p0 r1p1 might return corrupted data 1405548 CatC MSR DSPSR_EL0 while in debug r0p0, r1p0 r1p1 state might not correctly update PSTATE.{N,C,Z,V,GE} on debug exit 1415321 CatC LDREX-STREX might succeed r0p0, r1p0 r1p1 incorrectly when an intervening store occurs and LDREX detects a single-bit ECC error on the cache line in the L1 data cache tag RAM 1421023 CatC Portions of the branch target r0p0, r1p0 r1p1 address recorded in ETM trace information are incorrect for an indirect branch with a malformed branch target address 1487187 CatC Waypoints from previous r0p0, r1p0 r1p1 session might cause single-shot comparator match when trace enabled 1488613 CatC An unaligned load might initiate a r0p0, r1p0 r1p1 prefetch request which crosses a page boundary 1491015 CatC TRCIDR3.CCITMIN value is r0p0, r1p0 r1p1 incorrect 1514033 CatC Error Synchronization Barrier r0p0, r1p0 r1p1 (ESB) instruction execution with a pending masked Virtual SError might not clear HCR_EL2.VSE 1519163 CatC AMU Counter INST_RETIRED r0p0, r1p0 r1p1 does not increment correctly when 16 instructions retire in same cycle 1522097 CatC The core might detect a breakpoint r0p0, r1p0 r1p1 exception one instruction earlier than the programmed location when the L0 Macro-op cache contains an instruction that is affected by a parity error 1523503 CatC CPUECTLR_EL1 controls for the r0p0, r1p0 r1p1 MMU have no affect 1610369 CatC ERR0MISC0_EL1.SUBARRAY r0p0, r1p0, r1p1 Open value for ECC errors in the L1 data cache might be incorrect 1624431 CatC CPUAMEVTYPER4_EL0 register r0p0, r1p0 r1p1 cannot be written SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 15 of 59 Non-confidential 

16 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Errata descriptions Category A There are no errata in this category. Category A (rare) 1316063 Modification of the translation table for a virtual page which is being accessed by an active process might lead to read-after-write ordering violation Status Fault Type: Programmer Category A (Rare) Fault Status: Present in r0p0 and r1p0. Fixed in r1p1. Description If a virtual address for a cacheable mapping of a location is being accessed by a core while another core is remapping the virtual address to a new physical page using the recommended break-before-make sequence, then under rare circumstances TLBI+DSB completes before a write using the translation being invalidated has been observed by other observers. Configurations Affected The erratum affects all multi-core configurations. Conditions. 1. Core A has in program order a store (ST1) and a younger load (LD1) to the same cacheable virtual address. 2. Core B marks the associated translation table entry invalid, followed by a DSB; TLBI; DSB sequence which generates a sync request to Core A. 3. LD1 executes speculatively past ST1 and returns its result using the original physical address (PA1) under specific rare conditions before Core A has responded to the sync request. 4. At the time of receiving the sync request, on Core A: 1. No load younger than ST1 has executed out-of-order for any of the following instructions: 1. Load. 2. DMB. 3. DSB. 4. Atomic instruction which updates a register and has acquire semantics. 2. No store younger than ST1 has already computed its physical address (PA). 5. Any memory request from core A which was initiated prior to the sync request completes. 6. ST1 is not able to compute its PA before Core A responds to the sync request. 7. Core B receives the sync response and updates the translation table entry to map a new PA (PA2), which has write permissions and differs on bits [23:12] from PA1, followed by a DSB. 8. ST1 performs memory write using PA2 on Core A and commits the result from LD1 using PA1 because the read-after-write ordering violation between ST1 and LD1 is not detected. Implications If the above conditions are met under certain rare conditions, then this erratum might result in a read-after-write ordering violation. Workaround This erratum can be avoided by setting CPUACTLR2_EL1[16] to 1, hence preventing LD1 from speculating past ST1. This will have a performance impact on general workloads. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 16 of 59 Non-confidential 

17 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Category B 1160841 Continuous failing STREX because of another core snooping from speculatively executed atomic behind constantly mispredicted branch might cause livelock Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description Under certain conditions, a loop might continuously mispredict. If the speculative instruction path has an atomic instruction to the same physical address as another core's exclusive monitor address, then this might cause a repeatable loop where the cache line is requested by the atomic instruction to be unique, opening the exclusive monitor on the other core. Configurations Affected The erratum affects all configurations. Conditions 1. There is a loop that has a branch that is consistently mispredicted. 2. There is an atomic instruction outside of the loop that has the same physical address as the exclusive monitor address of another core, within a cache line. The atomic instruction makes a unique request, snooping that cache line from other cores, and opening the exclusive monitor. Implications If the above conditions are met, the core might livelock. Workaround Set CPUACTLR2_EL1[0] to 1 and CPUACTLR2_EL1[15] to 1. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 17 of 59 Non-confidential 

18 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1177367 Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description A speculative Address Translation (AT) instruction translates using registers associated with an out-of-context translation regime and caches the resulting translation in the L2 TLB. A subsequent translation request generated when the out- of-context translation regime is current uses the previous cached L2 TLB entry producing an incorrect virtual to physical mapping. Configurations Affected This erratum affects all configurations. Conditions 1. A speculative AT instruction performs a table walk translating virtual address to physical address using registers associated with an out-of-context translation regime. 2. Address translation data generated during the walk is cached in the L2 TLB. 3. The out-of-context translation regime becomes current and a subsequent memory access is translated using previously cached address translation data in the L2 TLB, resulting in an incorrect virtual to physical mapping. Implications If the above conditions are met, the resulting translation would be incorrect. Workaround When context-switching the register state for an out-of-context translation regime, system software at EL2 or above must ensure that all intermediate states during the context-switch would report a level 0 translation fault in response to an AT instruction targeting the out-of-context translation regime. Note that a workaround is only required if the system software contains an AT instruction as part of an executable page. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 18 of 59 Non-confidential 

19 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1191167 MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description Under certain internal timing conditions, an MRC instruction that closely follows an MRRC instruction might produce incorrect data when the MRRC is a read of specific Generic Timer system registers in AArch32 state. Configurations Affected This erratum affects all configurations. Conditions 1. The core is executing at AArch32 EL0. 2. An MRRC instruction which reads either the CNTPCT, CNTVCT, CNTP_CVAL, or CNTV_CVAL register is executed. 3. An MRC instruction is executed. Implications If this erratum occurs, then the destination register of the MRC is incorrect. Workarounds The erratum can be avoided by trapping MRC/MCR/MRRC/MCRR accesses in AArch32 to the affected registers and doing the equivalent code sequence in the trap handler. To trap the CNT* accesses, set CNTKCTL_EL1.{EL0PTEN, EL0VTEN, EL0VCTEN, EL0PCTEN} to 0. If HCR_EL2.{E2H,TGE}={1,1} then set CNTHCTL_EL2.{EL0PTEN, EL0VTEN, EL0VCTEN, EL0PCTEN} to 0. The following registers will be trapped: CNTP_CTL, CNTP_CVAL, CNTP_TVAL, CNTV_CTL, CNTV_CVAL, CNTV_TVAL, CNTPCT, CNTVCT, CNTFRQ. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 19 of 59 Non-confidential 

20 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1204882 The exclusive monitor might end up tracking an incorrect cache line in the presence of a VA-alias, causing a false pass on the exclusive access sequence Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description Under certain conditions, the exclusive monitor that tracks the Physical Address (PA) for the exclusive-access sequence, might end up tracking the incorrect way the cache line is in the L1 cache. As a result, a subsequent STREX might get a false pass, even though the cache line was written to by another master. Configurations Affected This erratum affects all configurations. Conditions 1. There is a load preceding the LDREX/STREX loop that has the same PA as the exclusive monitor address, within a cache line. However the load has a different VA, specifically a different VA[13:12] for 64KB L1 cache. 2. The LDREX issues ahead of this older load, misses the L1, and makes a request out to the L2 by allocating a request buffer. The L2 responds to the request for the LDREX, the line is allocated into the L1 cache, but the LDREX is prevented from picking up the response. 3. The older load subsequently misses the L1 and makes a request to the L2, using the same request buffer as that was previously used by the LDREX. 4. If the LDREX now replays, such that it coincides with the L2 response for the older load with the same PA, but a different VA, then it can forward from the L2 response for this load and complete. At this point, the exclusive monitor ends up capturing the way that this VA-aliased load is allocated into the L1, but the correct index that corresponds to the LDREX. 5. The exclusive monitor now ends up tracking the incorrect cache line. If the line was snooped out, it would therefore not transition to the open state. Implications If the above conditions are met, then the core might allow a subsequent STREX to pass, even though the LDREX/ STREX sequence was not atomic. Workaround This erratum can be avoided if software sets CPUACTLR2_EL1 bit[11] to 0b1. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 20 of 59 Non-confidential 

21 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1220737 Streaming store under specific conditions might cause deadlock or data corruption Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description Under certain rare conditions, a streaming write of at least 64 consecutive bytes might send only 32 bytes of data from the L1 data cache to higher level caches. Configurations Affected The erratum affects all configurations. Conditions 1. A store to address A is dispatched down a speculative path, before the write stream was engaged. 2. The write stream was engaged for a full cache line write. 3. A younger store instruction with address A is dispatched. Implications If the above conditions are met under certain timing conditions, then this erratum might result in deadlock or data corruption. Workaround This erratum can be avoided by setting CPUECTLR_EL1[25:24] to 0b11, which disables write streaming to the L2. This will have an impact on performance for streaming workloads. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 21 of 59 Non-confidential 

22 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1253791 Multiple floating-point divides/square roots concurrently completing back-to-back and flushing back-to-back might cause data corruption Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description Under certain conditions, two floating-point divide or square root instructions completing back-to-back and concurrently getting flushed by back-to-back branch mispredicts might result in data corruption. Configurations Affected This erratum affects all configurations. Conditions 1. Two or more concurrently executing floating-point divide and/or square root instructions need to complete in back-to-back cycles. 2. A branch mispredict arrives concurrently with the completion of the first divide. This divide will flush. 3. Another branch mispredict arrives concurrently with the completion of the second divide. This divide will flush. 4. No other floating-point/vector instructions are in the scheduler to be issued. 5. Newly dispatched instructions coincidentally pick up a register resource that was freed up by the last flushed divide. 6. The newly dispatched instruction gets issued before its producer is issued. Implications If the above conditions are met, then this erratum might result in data corruption. Workaround This erratum can be avoided by setting CPUACTLR3_EL1[10] to 1, which prevents parallel execution of divide and square root instructions. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 22 of 59 Non-confidential 

23 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1262841 Translation access hitting a prefetched L2 TLB entry under specific conditions might corrupt the L2 TLB leading to an incorrect translation Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description Under specific conditions, an incorrect virtual to physical mapping might happen because the L2 TLB is corrupted. The L2 TLB might be corrupted because of both: • A translation access hitting an entry in the L2 TLB which was previously allocated by the MMU hardware prefetch mechanism. • A TLBI VAAE1 or TLBI VAALE1 for a non-active VMID context invalidating an entry. A subsequent translation which hits against the corrupted entry generates an incorrect translation. Configurations Affected This erratum affects all configurations. Conditions 1. Virtualization is enabled. 2. The MMU hardware prefetcher installs an entry in the L2 TLB. 3. A translation request in the current VMID context hits on the prefetched entry. 4. TLBI VAAE1 or TLBI VAALE1 targeting a page within a non-active VMID context is in the process of invalidating a page. Implications If the above conditions are met, then the MMU might generate an incorrect translation. Workaround This erratum can be avoided by setting CPUECTLR_EL1[51] to 1, which disables the MMU hardware prefetcher. Setting this bit might have a small impact on performance. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 23 of 59 Non-confidential 

24 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1273521 A T32 instruction inside an IT block followed by a mispredicted speculative instruction stream might cause a deadlock Status Fault Type: Programmer Category B Fault Status: Present in r0p0. Fixed in r1p0. Description The core might hang when it executes a T32 instruction inside an IT block. Configurations Affected This erratum affects all configurations. Conditions 1. A T32 instruction is inside an IT block. 2. Subsequent instructions repeatedly create branch misprediction. Branch predictor misprediction occurs either because: 1. Address translation is disabled. 2. The second half of the T32 instruction can be decoded as 16-bit instruction updating R15 (PC). 3. Branch predictor RAMs have soft errors. 3. Another IT block instruction is fetched from the speculative instruction stream (that is corrected by the above branch misprediction) and executed before the first T32 instruction is retired from pipeline. Implications If the above conditions are met, the core might deadlock as the instruction in the IT block does not complete. Workaround This erratum can be avoided by setting CPUACTLR_EL1[13] to 1 to increase the mispredict to fetch latency, which will have some impact on performance. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 24 of 59 Non-confidential 

25 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1450698 Software Step might prevent interrupt recognition Status Fault Type: Programmer Category B Fault Status: Present in r0p0, r1p0. Fixed in r1p1. Description The Software Stepping of a system call instruction (SVC, HVC, or SMC) can prevent recognition of subsequent interrupts when Software Stepping is disabled in the exception handler of the system call. Additionally, unconventional code involving the Software Stepping of an MSR instruction that clears the MDSCR_EL1.SS bit (disables Software Step while stepping) can prevent recognition of subsequent interrupts. Configurations Affected This erratum affects all configurations. Conditions: Case A: 1. Software Step is enabled. 2. The system configuration is (MDSCR_EL1.KDE==1) or (MDSCR_EL1.KDE==0 and HCR_EL2.E2H==1 and (HCR_EL2.TGE==1 or MDCR_EL2.TDE==1)). 3. An ERET with SPSR_ELx.SS==1 is executed to cause the Software Step state machine to enter the active- not-pending state. 4. A system call instruction (SVC, HVC, or SMC) is executed and generates its system call exception (that is, it is not trapped). 5. The exception handler of the system call disables Software Step by clearing MDSCR_EL1.SS or by setting SPSR_ELx.D such that, upon return, no Software Step exception is taken. Case B: 1. Software Step is enabled. 2. An ERET with SPSR_ELx.SS==1 is executed to cause the Software Step state machine to enter the active- not-pending state. 3. An MSR MDSCR_EL1 instruction that clears the MDSCR_EL1.SS bit is executed (disables Software Step). Implications Case A: Arm believes that for this product, MDSCR_EL1.KDE is not set to 1 by deployed devices in the field and is only used when debugging the system software during initial product development. In these cases, the effect of the erratum is for interrupts to be disabled even after switching to other software contexts that are not being debugged as part of the system software debugging. Arm believes that a workaround does not need to be deployed for the situation where MDSCR_EL1.KDE==1, and a workaround is not available. Some devices are expected to run an operating system at EL2 with HCR_EL2.E2H set to 1. The implication of this erratum for such a system is that single-stepping of an untrusted user application at EL0 can lead to subsequent execution not recognizing interrupts where it should, leading to errant behavior. The software workaround described below can be deployed in the operating system at EL2 to prevent single-stepping of untrusted user applications from triggering this erratum. Case B: Unconventional code involving the Software Stepping of the disabling instruction is not expected to be encountered, therefore no workaround is required. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 25 of 59 Non-confidential 

26 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 Workaround When Software Step is used to debug an application under an operating system running at EL2 with HCR_EL2.E2H set to 1, the software workaround involves explicitly triggering a Software Step exception with modifications to the system call exception handler code and Software Step exception handler code. This entails setting MDSCR_EL1.KDE and MDSCR_EL1.SS and clearing PSTATE.D to trigger a Software Step exception from the system call handler. The Software Step handler then sets SPSR_ELx.D before returning back to the system call handler, where MDSCR_EL1.KDE and MDSCR_EL1.SS are restored to their original values. If a workaround is required when MDSCR_EL1.KDE is set to 1, then please contact Arm. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 26 of 59 Non-confidential 

27 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1467687 Branch prediction for an ERET cached in the instruction cache might cause a deadlock Status Fault Type: Programmer Category B Fault Status: Present in r0p0 and r1p0. Fixed in r1p1. Description When a branch predictor makes a prediction for an ERET instruction, the core might deadlock. Configurations Affected This erratum affects all configurations. Conditions 1. The core executes a conditional branch instruction. 2. The branch predictor caches the branch in Condition 1. 3. The branch instruction is overwritten by an ERET instruction by a self-modifying code sequence. 4. The core caches the ERET instruction in the instruction cache, and later fetches the ERET instruction from the cache. 5. The branch predictor makes a prediction for the ERET based on the branch information cached at Condition 2. 6. The predicted target matches ELR[PSTATE.EL]. Implications If the above conditions are met, then the core might deadlock. Workaround This erratum can be avoided by preventing the caching of the ERET. This can be done through the following write sequence to several IMPLEMENTATION DEFINED registers: LDR x0,=0x3 MSR S3_6_c15_c8_0,x0 LDR x0,=0xF3D08000 MSR S3_6_c15_c8_2,x0 LDR x0,=0xFFF0F0FF MSR S3_6_c15_c8_3,x0 LDR x0,=0x80000002003FF MSR S3_6_c15_c8_1,x0 ISB SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 27 of 59 Non-confidential 

28 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1508412 NC/Device Load and Store Exclusive or PAR-Read collision can cause deadlock Status Fault Type: Programmer Category B Fault Status: Present in r0p0, r1p0. Fixed in r1p1. Description Under certain conditions, execution of either a load to device or non-cacheable memory, and either a store exclusive or register read of the PAR (physical address register), in close proximity might lead to a deadlock. Configurations Affected This erratum affects all configurations. Conditions 1. Execution of any load with device or non-cacheable memory attributes, and 2. Execution of a store-exclusive or register read of PAR. Implications If the above conditions are met, then the core might stop executing code. Workaround This erratum can be avoided by having the hardware insert a DMB SY before and after accessing PAR_EL1 and inserting a DMB SY before and after a store-exclusive instruction. This can be done through the following write sequence to several IMPLEMENTATION DEFINED registers. The code sequence should be applied early in the boot sequence prior to any of the possible errata conditions being met. LDR x0,=0x0 MSR S3_6_c15_c8_0,x0 LDR x0,= 0xEE070F14 MSR S3_6_c15_c8_2,x0 LDR x0,= 0xFFFF0FFF MSR S3_6_c15_c8_3,x0 LDR x0,=0x4005003FF MSR S3_6_c15_c8_1,x0 LDR x0,=0x1 MSR S3_6_c15_c8_0,x0 LDR x0,=0x00e8400000 MSR S3_6_c15_c8_2,x0 LDR x0,=0x00fff00000 MSR S3_6_c15_c8_3,x0 LDR x0,= 0x4005007FF MSR S3_6_c15_c8_1,x0 LDR x0,=0x2 MSR S3_6_c15_c8_0,x0 LDR x0,=0x00e8c00040 MSR S3_6_c15_c8_2,x0 LDR x0,=0x00fff00040 MSR S3_6_c15_c8_3,x0 LDR x0,= 0x4005007FF MSR S3_6_c15_c8_1,x0 ISB SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 28 of 59 Non-confidential 

29 .Date of issue: 08-Nov-2019 Arm Cortex-A77 MP074 Software Developer Errata Notice Version: 9.0 1515815 The core might execute multiple instructions before taking a software step exception or halt step exception when the executing instruction resides in the L0 Macro-op cache Status Fault Type: Programmer Category B Fault Status: Present in r0p0, r1p0. Fixed in r1p1. Description When the core executes an instruction during an active-not-pending state in a software step or halt step process, the core might execute multiple instructions before taking a software step exception or halt step exception. Configurations Affected This erratum affects all configurations. Conditions 1. Software step or halt step is enabled in the AArch64 instruction state. 2. Instruction fetch hits in the L0 Macro-op cache. Implications If the above conditions are met, then the core might execute multiple instructions before taking a software step exception or halt step exception. Workaround Set CPUACTLR_EL1[11] to one, which flushes the L0 Macro-op cache for all context synchronization events. Category B (rare) 1286809 Modification of the translation table for a virtual page which is being accessed by an active process might lead to read-after-read ordering violation Status Fault Type: Programmer Category B (Rare) Fault Status: Present in r0p0, r1p0. Fixed in r1p1. Description If a virtual address for a cacheable mapping of a location is being accessed by a core while another core is remapping the virtual address to a new physical page using the recommended break-before-make sequence, then under very rare circumstances TLBI+DSB completes before a read using the translation being invalidated has been observed by other observers. Configurations Affected The erratum affects all multi-core configurations. Conditions 1. Core A speculatively executes a load (LD2) ahead of an older load (LD1) to the same cacheable virtual address. SDEN-1152370 Copyright © 2019, Arm Limited or its affiliates. All rights reserved. Page 29 of 59 Non-confidential